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S i 4 3 11
315/433.92 MH Z FSK RECEIVER
Features

Single chip receiver with only six external components Selectable 315/433.92 MHz carrier frequency Supports FSK modulation High sensitivity (-104 dBm @ 5 kbps) Excellent interference rejection Selectable IF bandwidths Automatic Frequency Centering (AFC)
Data rates up to 10 kbps Direct battery operation with onchip low drop out (LDO) voltage regulator 16 MHz crystal oscillator support 3x3x0.85 mm 20L QFN package (RoHS compliant) -40 to +85 C temperature range
Applications

Ordering Information: See page 14.
Satellite set-top box receivers Remote controls, IR replacement/extension Garage and gate door openers Home automation and security

Remote keyless entry After market alarms Telemetry Wireless point of sale Toys
Pin Assignments SI4311 (Top View)
DEV0 17 10 XTL2 DEV1 16 15 BT0 14 BT1 13 DOUT 12 GND 7 GND 8 VDD 9 XTL1 11 VDD NC NC 19 NC 18
Description
The SI4311 is a fully-integrated FSK CMOS RF receiver that operates in the unlicensed 315 and 433.92 MHz ultra high frequency (UHF) bands. It is designed for high-volume, cost-sensitive RF receiver applications, such as set-top box RF receivers, remote controls, garage door openers, home automation, security, remote keyless entry systems, wireless POS, and telemetry. The SI4311 offers industry-leading RF performance, high integration, flexibility, low BOM, small board area, and ease of design. No production alignment is necessary as all RF functions are integrated into the device.
VDD 1 RFGND 2 RX_IN 3 RST 4 AFC 5 6 315/434
20
GND PAD
Functional Block Diagram
Antenna RX_IN LNA AGC 2.7 - 3.6 V VDD GND LDO AFC XTAL OSC PGA ADC ADC
SI4311
DOUT DSP MCU BASEBAND PROCESSOR SQUELCH
Patents pending
AFC 315/434 DEV[1:0] BT[1:0] RST
16 MHz
Rev. 0.5 3/10
Copyright (c) 2010 by Silicon Laboratories
SI4311
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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SI4311 TABLE O F CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1. Typical Application Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. Receiver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. Carrier Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4. Bit Time BT[1:0] Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5. Frequency Deviation Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6. Automatic Frequency Centering (AFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.7. Low Noise Amplifier Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.9. Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. Pin Descriptions: SI4311-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1. SI4311 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. Package Outline: SI4311-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. PCB Land Pattern: SI4311-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
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1. Electrical Specifications
Table 1. Recommended Operating Conditions*
Parameter Supply Voltage Supply Voltage Powerup Rise Time Ambient Temperature Symbol VDD VDD-RISE TA Test Condition Min 2.7 10 -40 Typ 3.3 -- 25 Max 3.6 -- 85 Unit V s C
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter Supply Voltage Input Current3 Input Voltage3 Operating Temperature Storage Temperature RF Input Level4 Symbol VDD IIN VIN TOP TSTG Value -0.5 to 3.9 10 -0.3 to (VDD + 0.3) -45 to 95 -55 to 150 0.4 Unit V mA V C C VPK
Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The SI4311 device is a high-performance RF integrated circuit with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For input pins 315/434, AFC, BT[1:0], and DEV[1:0]. 4. At RF input pin RX_IN.
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Table 3. DC Characteristics
(TA = 25 C, VDD = 3.3 V, Rs = 50 , FRF = 433.92 MHz unless otherwise noted)
Parameter Supply Current Reset Supply Current High Level Input Voltage
1
Symbol IVDD IRST VIH VIL IIH IIL
2
Test Condition
Min --
Typ 20 2 -- -- -- -- -- --
Max -- TBD VDD + 0.3 0.3 x VDD 10 10 -- 0.2 x VDD
Unit mA A V V A A V V
Reset asserted
-- 0.7 x VDD -0.3
Low Level Input Voltage1 High Level Input Current
1
VIN = VDD = 3.6 V VIN = 0 V, VDD = 3.6 V IOUT = 500 A IOUT = -500 A
-10 -10 0.8 x VDD --
Low Level Input Current1 High Level Output Voltage Low Level Output Voltage2
VOH VOL
Notes: 1. For input pins 315/434, AFC, BT[1:0], and DEV[1:0]. 2. For output pin DOUT.
Table 4. Reset Timing Characteristics
(VDD = 3.3 V, TA = 25 C)
Parameter RST Pulse Width
Symbol tSRST
Min 100
Typ --
Max --
Unit s
tSRST
RST
70% 30%
Figure 1. Reset Timing
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Table 5. SI4311 Receiver Characteristics
(TA = 25 C, VDD = 3.3 V, Rs = 50 , FRF = 433.92 MHz unless otherwise noted)
Parameter
Symbol
Test Condition 1.0 kbps, f = 50 kHz, xtal = 20 ppm, 315 MHz (Note 2) 10 kbps, f = 50 kHz, xtal = 20 ppm, 315 MHz (Note 2) 1.0 kbps, f = 50 kHz, xtal = 20 ppm, 433.92 MHz (Note 2) 10 kbps, f = 50 kHz, xtal = 20 ppm, 433.92 MHz
Min -- -- -- TBD --
Typ -104 -101 -102 -100 --
Max -- -- -- -- 10
Unit dBm dBm dBm dBm kbps
Sensitivity @ BER =
10-3 (Note 1)
Data Rate3
Adjacent Channel Rejection 200 kHz1
Desired signal is 3 dB above sensitivity (BER = 10-3), unmodulated interferer is at 200 kHz, rejection measured as TBD difference between desired signal and interferer level in dB when BER = 10-3 Desired signal is 3 dB above sensitivity (BER = 10-3), unmodulated interferer is at 400 kHz, rejection measured as difference between desired signal and interferer level in dB when BER = 10-3
35
--
dB
Alternate Channel Rejection 400 kHz1,2 Image Rejection, IF = 128 kHz1,2
--
55
--
dB
-- 2 MHz, 2.4 kbps, desired signal is 3 dB above sensitivity, CW interferer level is increased until BER = 10-3 10 MHz, 2.4 kbps, desired signal is 3 dB above sensitivity, CW interferer level is increased until BER = 10-3 --
35 65
-- --
dB dB
Blocking1,2
-- --
70 8
-- --
dB dBm
Maximum RF Input Power 1,2 Input IP33 FSK Deviation Input Range3 LNA Input Capacitance RX Boot Time3
3
| f2 - f1 | = 5 MHz, high gain mode, desired signal is 3 dB above sensitivity, CW interference levels are increased until BER = 10-3
--
-10
--
dBm
10 -- From reset --
-- 7 320
90 -- --
kHz pF ms
Notes: 1. 1.0 kbps, f = 50 kHz, xtal = 20 ppm, AFC = 0, BT[1:0] = 00, DEV[1:0] = 01. 2. Guaranteed by characterization. 3. Guaranteed by design.
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Table 6. Crystal Characteristics
(VDD = 3.3 V, TA = 25 C)
Parameter Crystal Oscillator Frequency Crystal ESR XTL1, XTL2 Input Capacitance
Symbol
Test Condition
Min -- -- --
Typ 16 -- 11
Max -- 100 --
Unit MHz pF
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2. Typical Application Schematic
DEV0 20 19 18 17 16 DEV1 BT0 BT1 BT0 BT1 DOUT GND 15 14 13 12 VDD C1 22 nF RX ANTENNA
L1 C3 C2 1 uF
1 VDD 2 RFGND 3 U1 RX_IN SI4311-GM 4 RST 5 AFC
GND PAD
NC NC NC DEV0 DEV1
VDD
DOUT VBATTERY 2.7 to 3.6 V
VDD 11
R1 20 k
AFC X1 (16 MHz)
Figure 2. SI4311 FSK 433.92 MHz Application Schematic
2.1. Typical Application Bill of Materials
Table 7. SI4311 Typical Application Bill of Materials
Component(s) C1 C2 C3 L1 R1 X1 U1 Value/Description Supply bypass capacitor, 22 nF, 20%, Z5U/X7R Time constant capacitor, 1 F Antenna matching capacitor, 15 pF Antenna matching inductor, 33 nH for 433.92 MHz and 62 nH for 315 MHz Time constant resistor, 20 k 16 MHz crystal SI4311 315/433.92 MHz FSK receiver Supplier(s) Murata Murata Murata Murata Murata Hosonic Silicon Laboratories
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6 7 8 9 10
Rev. 0.5
434 GND VDD XTL1 XTL2
SI4311
3. Functional Description
3.1. Overview
Antenna RX_IN LNA AGC 2.7 - 3.6 V VDD GND LDO AFC XTAL OSC PGA ADC ADC
SI4311
DOUT DSP MCU BASEBAND PROCESSOR SQUELCH
AFC 315/434 DEV[1:0] BT[1:0] RST
16 MHz
Figure 3. Functional Block Diagram
The SI4311 is a fully-integrated FSK CMOS RF receiver that operates in the unlicensed 315 and 433.92 MHz ultra high frequency (UHF) bands. It is designed for high-volume, cost-sensitive RF receiver applications. The chip operates at a carrier frequency of 315 or 433.92 MHz and supports FSK digital modulation with data rates of up to 10 kbps. The device leverages Silicon Labs' patented and proven digital low-IF architecture and offers superior sensitivity and interference rejection. The SI4311 can achieve superior sensitivity in the presence of large interference due to its high dynamic range ADCs and digital filters. The digital low-IF architecture also enables superior blocking ability and low intermodulation distortion for robust reception in the presence of wide-band interference. Digital integration reduces the number of required external components compared to traditional offerings, resulting in a solution that only requires a 16 MHz crystal and passive components allowing a small and compact printed circuit board (PCB) implementation area. The high integration of the SI4311 improves the system manufacturing reliability, improves quality, eases design-in, and minimizes costs.
3.2. Receiver Description
The RF input signal is amplified by a low-noise amplifier (LNA) and down-converts to a low intermediate frequency with a quadrature image-reject mixer. The mixer output is amplified by a programmable gain amplifier (PGA), filtered, and digitized with a highresolution analog-to-digital converter (ADC). All RF functions are integrated into the device eliminating any production alignment issues associated with external components, such as SAW and ceramic IF filters. Silicon Labs' advanced digital low-IF architecture achieves superior performance by using the DSP to perform channel filtering, demodulation, automatic gain control (AGC), automatic frequency control (AFC), and other baseband processing. DSP implementation of the channel filters provides better repeatability and control of the bandwidth and frequency response of the filter compared to analog implementations. No off-chip ceramic filters are needed with the SI4311 since all IF channel filtering is performed in the digital domain.
3.3. Carrier Frequency Selection
The SI4311 can be tuned to either 315 or 433.92 MHz by driving Pin 6 (315/434) to VDD or GND. The 315 MHz operation is chosen by driving Pin 6 (315/434) to VDD, and 433.92 MHz operation is chosen by driving Pin 6 (315/434) to GND.
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Table 8. Carrier Frequency Selection
Pin 6 (315/434) 0 1 Frequency [MHz] 433.92 315
3.4. Bit Time BT[1:0] Selection
The SI4311 can operate with data rates of up to 10 kbps non-return to zero (NRZ) data or 5 kbps Manchester encoded data. However, FSK modulation uses other encoding schemes, such as pulse width modulation (PWM) and pulse position modulation (PPM) in which a bit can be encoded into a pulse with a certain duty cycle or pulse width (see Figure 4).
Digital Data NRZ Encoding Manchester Encoding PPM Encoding
"1"
"0"
"1"
"1"
100 us 1000 us
Figure 4. Example Data Waveforms
In order to set the data filter bandwidth correctly, the shortest pulse width of the transmitted encoded data should be chosen as the bit time. In the PPM example shown in Figure 4, the shortest pulse width is 100 s, so the bit time is chosen as BT = 100 s even though the actual data rate is 1 kbps (1000 s). After finding BT, Table 9 can be used to find the bit settings for pins 14 and 15, BT[1:0]. In this PPM example, BT[1:0] is set as logic BT1 = 1 and BT0 = 1 or BT[1:0] = (1,1) since BT = 100 s.
Table 9. How to Choose BT[1:0] Based on the Bit Time
Bit Time [us] BT 1000 1000< BT 500 500 < BT 200 200 < BT 100 BT1 (pin 14) 0 0 1 1 BT0 (pin 15) 0 1 0 1
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3.5. Frequency Deviation Selection
In order to accommodate wide frequency deviation ranges, the SI4311 FSK receiver uses two input pins, pins 16 and 17, to select a range of frequency deviations as shown in Table 10. For example, if the FSK signal has a frequency deviation (F) of 50 kHz, then the DEV[1:0] = (0,1) or pin 16 = 0 and pin 17 = 1.
Table 10. Frequency Deviation Range Settings
DEV1 (pin 16) 0 0 1 1 DEV0 (pin 17) 0 1 0 1 Frequency Deviation [kHz] 1 < F 30 30 < F 50 50 < F 70 70 < F 90
3.6. Automatic Frequency Centering (AFC)
The channel bandwidth directly affects the sensitivity of any wireless receiver. Typical analog FSK receivers use an external ceramic filter with a large bandwidth to accommodate the data rate, frequency deviation, crystal tolerances, and transmit carrier frequency offsets, which leads to unnecessary amounts of noise and lower sensitivity levels. The SI4311 uses a narrow channel bandwidth of 200 kHz and automatic frequency centering (AFC) to obtain excellent sensitivity levels (-104 dBm at data rate of 5 kbps at 315 MHz) while still accommodating up to 200 kHz of frequency tracking from its center frequency.
IF BW 200kHz TX OFFSET 100kHz TX OFFSET 100kHz
(a)
(b)
(c)
Figure 5. (a) Ideal case (b) Scenario with Tx Offset (c) SI4311 AFC Re-Centers IF BW
In the ideal case of no transmit carrier frequency errors or receiver frequency errors, both FSK tones for a logic "1" and "0" from the transmitter appear in the receiver IF channel bandwidth as shown in Figure 5 (a). However, if the transmitter has a large carrier offset such as shown in Figure 5 (b), then only one of the FSK tones falls in the receiver channel bandwidth and thus the receiver produces errors. The standard approach to resolving this problem is to use an IF channel filter that is large enough to accommodate the transmitter frequency error, but this leads to degraded sensitivity. The SI4311 uses AFC to re-center the channel bandwidth about the two FSK tones as shown in Figure 5 (c) to maintain excellent sensitivity with a small IF channel filter. The algorithm requires one FSK tone to be in-band and at most three alternating sequences of 0/1 data typically found in a preamble plus 700 s of fixed delay time (approximately 230 s per 0/1 data pair) to re-center the IF bandwidth. Worst case acquisition time is 1.3 ms for a data rate of 10 kbps. The AFC algorithm includes a 200 ms hold time. The device holds the frequency found by the AFC algorithm for a time of 200 ms after no RF signal activity before restarting the frequency search. This allows a frequency found in the first packet of transmission to be held for any subsequent retransmissions of packets if the retransmissions occur before 200 ms. This hold frequency ensures all bits of the second and subsequent packets are recovered completely. The AFC frequency search resumes after 200 ms of no RF signal activity. The AFC algorithm can be disabled by setting the logic level on pin 5 to a logic zero as shown in Table 11.
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Table 11. AFC Selection Pin 5
Pin 5 0 1 AFC Disable Enable
3.7. Low Noise Amplifier Input Circuit
Figure 2 shows the typical application circuit with 50 matching. Components C3 and L1 are used to transform the input impedance of the LNA. C3 is equal to 15 pF and L1 is equal to 33 nH at 433.92 MHz and 62 nH at 315 MHz for 50 matching.
3.8. Crystal Oscillator
An on-board crystal oscillator is used to generate a 16 MHz reference clock for the SI4311. This reference frequency is required for proper operation of the SI4311 and is used for calibration of the on-chip VCO and other timing references. No external load capacitors are required to set the 16 MHz reference frequency if the recommended crystal load capacitor is around 14 pF, assuming the effective board capacitance between pins XTL1 and XTL2 is 3 pF and the chip input capacitance on pins XTL1 or XTL2 is 11 pF. Refer to Table 6, "Crystal Characteristics," on page 7 for board capacitance and frequency tolerance information. The frequency tolerance of the crystal should be chosen such that the received signal is within the IF bandwidth of the SI4311 receiver. Additionally, the SI4311 can be driven by an external 16 MHz reference clock. The clock signal can be applied to either the XTL1 or XTL2 inputs. When the 16 MHz reference clock is applied to one of the inputs, the other crystal input pin must be floating.
3.9. Reset Pin
Driving the RST pin (pin 4) low will disable the SI4311 and place the device into reset mode. All active blocks in the device are powered off in this mode, bringing the current consumption to <10 uA. The SI4311 is enabled by driving the RST pin (pin 4) to VDD. Refer to Table 4 "Reset Timing Characteristics" for the reset timing requirements. The chip requires about 320 ms to go from reset to active mode. The SI4311 can output invalid data during the 320 ms turn-on time.
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SI4311
4. Pin Descriptions: SI4311-B10-GM
DEV0 17 10 XTL2
VDD
1
20
19
18
RFGND 2 RX_IN 3 RST 4 AFC 5 6 315/434 7 GND 8 VDD 9 XTL1
GND PAD
Pin Number(s) 1, 8, 11 2 3 4 5 6 7, 12, GND PAD 9 10 13 14, 15 16,17 18,19,20
Name VDD RFGND RX_IN RST AFC 315/434 GND XTL1 XTL2 DOUT BT[1:0] DEV[1:0] NC
Description Supply voltage, may connect to external battery. RF ground. Connect to ground plane on PCB. RF receiver input. Device reset, active low input. AFC selection input pin. Selectable logic input for 315 or 433.92 MHz operation. Ground. Connect to ground plane on PCB. Crystal input. Crystal input. Data output. Bit time selection input pins. Frequency deviation input pins. No connect. Leave floating.
Rev. 0.5
DEV1 16 15 BT0 14 BT1 13 DOUT 12 GND 11 VDD
NC
NC
NC
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5. Ordering Guide
Part Number* SI4311-B10-GM Description 315/433.92 MHz FSK Receiver Package Type QFN Pb-free Operating Temperature -40 to 85 C
*Note: Add an "(R)" at the end of the device part number to denote tape and reel option.
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SI4311
6. Package Markings (Top Marks)
6.1. SI4311 Top Mark
Figure 6. SI4311 Top Mark Example
6.2. Top Mark Explanation
Mark Method: Line 1 Marking: Line 2 Marking: Line 3 Marking: YAG Laser Part Number Firmware Revision Die Revision TTT = Internal Code 11 = SI4311 10 = Firmware Revision 1.0 B = Revision B Die Internal tracking code
Circle = 0.5 mm Diameter Pin 1 Identifier (Bottom-Left Justified) YWW = Date Code Assigned by the Assembly House. Corresponds to the last digit of the current year (Y) and the workweek (WW) of the mold date.
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Si4 311
7. Package Outline: SI4311-B10-GM
Figure 7 illustrates the package details for the SI4311-B10-GM. Table 12 lists the values for the dimensions shown in the illustration.
Figure 7. 20-Pin Quad Flat No-Lead (QFN) Table 12. Package Dimensions
Symbol Min A A1 b c D D2 e E E2 1.65 1.65 0.80 0.00 0.20 0.27 Millimeters Nom 0.85 0.02 0.25 0.32 3.00 BSC 1.70 0.50 BSC 3.00 BSC 1.70 1.75 1.75 Max 0.90 0.05 0.30 0.37 f L L1 aaa bbb ccc ddd eee 0.30 0.00 -- -- -- -- -- Symbol Min Millimeters Nom 2.53 BSC 0.35 -- -- -- -- -- -- 0.40 0.10 0.05 0.05 0.08 0.10 0.10 Max
Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
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SI4311
8. PCB Land Pattern: SI4311-B10-GM
Figure 8 illustrates the PCB land pattern details for the SI4311-B10-GM. Table 13 lists the values for the dimensions shown in the illustration.
Figure 8. PCB Land Pattern
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Table 13. PCB Land Pattern Dimensions
Symbol Millimeters Min D D2 e E E2 f GD 1.60 Max GE W X Y ZE ZD -- -- -- 1.80 Symbol Millimeters Min 2.10 -- -- Max -- 0.34 0.28 0.61 REF 3.31 3.31
2.71 REF 0.50 BSC 2.71 REF 1.60 2.10 1.80 2.53 BSC
Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification. 3. This land pattern design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a fabrication allowance of 0.05 mm. Solder Mask Design 5. All metal pads are to be non-solder-mask-defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component standoff. Card Assembly 10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components.
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SI4311
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Revision 0.3 to Revision 0.4

Maximum data rate changed from 10 to 4 kbps for FSK and from 5 to 2 kbps for OOK with Manchester encoding. Maximum RF input power changed from 5 to 10 dBm. Changed test conditions for sensitivity measurements and added the xtal frequency tolerance of 20 ppm. Updated text in section "3. Functional Description". Added Ideal IF Bandwidth equation and description for choosing the IF bandwidth in Section "3.4. Bit Time BT[1:0] Selection". Updated Table 11, "Typical Sensitivity @ 433 MHz, 2-FSK," on page 11. Changed hysteresis level from 1 dB to 6 dB in Section "3.8. Crystal Oscillator". Added text in section "3.8. Crystal Oscillator" regarding the crystal frequency tolerance and IF Bandwidth choice and sensitivity performance.

Removed crystal frequency tolerance range from Table 6 "Crystal Characteristics". Corrected data rates in Section "3.1. Overview". Updated text in section "3.4. Bit Time BT[1:0] Selection" to show FSK receive IF bandwidth equations. Deleted voltage gain text in section "3.7. Low Noise Amplifier Input Circuit". Removed squelch circuit description in section "3.8. Crystal Oscillator". Included load capacitance requirement for crystal if no external capacitors are used in section "3.8. Crystal Oscillator". Added reset to active time in section "3.9. Reset Pin". Changed ordering guide part number in section "5. Ordering Guide". Added FSK Automatic Frequency Calibration information Removed OOK feature.
Revision 0.2 to Revision 0.3

Revision 0.4 to Revision 0.5

Updated features list Reduced font size in the test condition section of Table 5 "SI4311 Receiver Characteristics" Added crystal tolerance equation to Table 6 "Crystal Characteristics" Updated matching circuit and BOM to section "2. Test Circuit" and section "2. Typical Application Schematic" Modified text in Section "3. Functional Description" Changed bandwidth option in Table 11 "Bandwidth Selection Table Using BW[3:1] Pins" and test mode. Reset section updated to reflect active blocks are powered off in reset mode.
Removed IVDD current spec when input = -30 dBm from Table 3 "DC Characteristics" Updated sensitivity specs and test conditions in Table 5 "SI4311 Receiver Characteristics" Added AFC hold time description to section "3.6. Automatic Frequency Centering (AFC)" Added reference clock drive capability to section "3.8. Crystal Oscillator"
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CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: wireless@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Price & Availability of SI4311

	To Download SI4311 Datasheet File
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